The invention relates to a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which component comprises a non-volatile storage cell in the form of a MOS field effect transistor with a transistor gate and a MOS capacitor with a capacitor gate. The invention further relates to a system comprising a charge detector semiconductor component and a reference semiconductor component. The invention further relates to a wafer as well as to the use of a wafer with a number of charge detector semiconductor elements and/or systems. Finally, the invention relates to a method for the qualitative and quantitative measurement of charging of a wafer during processing of the wafer.
Wafer charging is a phenomenon that takes place continuously during the manufacture of semiconductor components, because many process steps take place in a plasma or are carried out by means of charged particles. In particular the thin gate oxides of MOS transistors in CMOS-type technologies, i.e. CMOS or BICMOS or similar technologies, can be destroyed by the charge collected on conductive surfaces, for example made of polycrystalline silicon or metal, during a process step and by the resulting tunnel current. This charging often is a cause of a low production yield.
It is attempted in product development to reduce the influence of the charging on the yield by means of so-called antenna rows.
During the process, test wafers are used, so-termed CHARM wafers (CHARging Monitors), in attempts to identify those process steps and pieces of equipment which cause particularly much charging and accordingly low yields.
Process monitoring by means of a CHARM wafer, however, is complicated and expensive, in particular because a production is to be interrupted for measuring one or several CHARM wafers.
JP-10-284726 describes a structure consisting of a p-channel and an n-channel MOS transistor and a method of measuring wafer charging in surroundings comprising a plasma. The structure requires a measurement before and after the plasma process step. This is only possible if the structure is contacted. This means that the monitoring of production goods having the structure can definitely be used for plasma steps at the end of a manufacturing process.
U.S. Pat. No. 5,959,309 describes a structure comprising an antenna, a diode string, a reverse-biased and a forward-biased transistor, and a storage capacitor for measuring wafer charging in surroundings comprising a plasma. A method in which the finished structure is placed in an instantaneous state in a plasma arrangement is also described therein. After completion of the plasma process, the end state is read out and compared with the original instantaneous state. A measure for charging in the step just carried out can be derived from the measured difference. An installation can be monitored by this method. The monitoring, however, cannot be carried out during the manufacture of useful material.
The methods of the two publications cited above have a number of disadvantages. Thus the expensive manufacturing installations are not operative during the monitoring of wafer charging. The production break causes considerable expense.
Furthermore, expensive test wafers such as those known, for example, as CHARM wafers, are required for monitoring.
Finally, the installation is checked at one particular moment only. The ongoing production, however, remains unchecked during this.
The structures described in JP-10-284726 and U.S. Pat. No. 5,959,309, furthermore, do not render possible a very accurate assessment of the charging. In particular, no analysis of any individual process step is possible.
Furthermore, the structures are not compatible with the CMOS manufacturing processes because they have no construction of the CMOS technology type and no circuits of the CMOS technology type, so that a number of process steps is necessary outside the CMOS technology standard. Thus it may be noted that the structure of JP 10-284726 is not compatible with the standard CMOS manufacturing method because it uses two polycrystalline silicon levels (4 and 3 in FIG. 3). The structure of U.S. Pat. No. 5,959,309 is not compatible with the standard CMOS manufacturing method because on the one hand it uses a high-quality capacitor (46 in FIGS. 4a and 4b) which would be manufactured with two superimposed polycrystalline silicon levels as a rule in a CMOS process. As a result, an additional polycrystalline silicon level becomes necessary again as compared with the standard CMOS process. On the other hand, the photodiode string (43 in FIG. 4a) requires the layers lying over the photodiode to be transparent. This, however, need not necessarily be the case in a standard CMOS process. Furthermore, a silicon semiconductor may not be capable of absorbing plasma radiation over the entire spectral range that occurs. An application of the structures described therein to production goods within the scope of a CMOS wafer processing is accordingly impossible.
A non-volatile storage cell is known from the publication xe2x80x9cEEPROM-Struktur im CMOS-Technologie mit einer Polysiliciumebenexe2x80x9d (EEPROM Structure in CMOS Technology with One Polycrystalline Silicon Level), Shaker Verlag, ISBN 3-8265-3289-9, Aachen 1998, and from WO 00/60672, which can be manufactured in a standard CMOS process. It is not suitable, however, for use as a monitor for wafer charging, i.e. as a wafer charging detector device.
It is an object of the present invention to provide a structure which is based on a non-volatile storage structure and which operates as a process control monitor (PCM) structure. It is a further object to indicate a use of the structure and a method whereby the charge can be measured which has arisen in a given location on a wafer during a process step, which structure was manufactured during the manufacture and/or processing of the wafer in a CMOS or BICMOS technology.
To achieve the object as regards the structure, the invention in a first embodiment is based on a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which comprises a non-volatile storage cell in the form of
a MOS field effect transistor with a transistor gate, and advantageously also a source and a drain, and
a MOS capacitor with a capacitor gate, and advantageously also a source and a drain.
In such a charge detector semiconductor component, according to the invention, the following are provided:
an antenna which is in operational connection with the capacitor gate, wherein the capacitor gate is connected in a further operational connection to the transistor gate such that a charge arising on the antenna can be stored in the storage cell and can be retrieved upon demand, and wherein the structure is arranged in compatibility with the CMOS technology.
To achieve the object as regards the structure in a second embodiment, the invention offers the following:
a system comprising a charge detector semiconductor component and a reference semiconductor component, in the form of a structure provided on a semiconductor material, wherein the charge detector semiconductor component comprises a non-volatile detector storage cell in the form of
a first MOS field effect transistor with a detector transistor gate, and preferably also a source and a drain, and a first MOS capacitor with a detector capacitor gate, and preferably also a source and a drain, and comprises an antenna which is connected to the detector capacitor gate via
a first operational connection, wherein the detector capacitor gate is connected via a first operational connection, wherein the detector capacitor gate is connected to the detector transistor gate via a further first operational connection, and wherein
the reference semiconductor component comprises a non-volatile reference storage cell in the form of a second MOS field effect transistor with a reference transistor gate, and preferably also a source and a drain, and a second MOS capacitor with a reference capacitor gate, and preferably also a source and a drain,
and comprises a ground conductor which is connected to the reference capacitor gate via a second operational connection, while the reference capacitor gate is connected to the reference transistor gate via a further second operational connection.
The invention is here based on the recognition that it is possible to manufacture the structure in the first and the second embodiment in each and every CMOS/BICMOS standard process during the manufacture of the wafer. The structure accordingly has an arrangement in accordance with the CMOS technology, i.e. only those units are used in the structure which can also be manufactured in any CMOS/BICMOS standard process used. In particular, units such as NMOS and PMOS transistors are used. Such units are available in all CMOS processes. The above structure may thus be present on each and every production wafer without additional process steps being necessary.
Units requiring several polycrystalline silicon levels have been particularly avoided. A continuous monitoring of the charging effect in the ongoing manufacture is only possible with the PCM structure (process control monitor structure) suitable as described above, according to the recognition. Said PCM structure is capable of storing charge arising during the process implementation in a non-volatile manner. Accordingly, said PCM structure uses a non-volatile storage cell. Additional process steps are usually necessary for the manufacture of non-volatile storage cells, so that the implementation in a standard CMOS or BICMOS technology or a similar technology has not been possible until now. Additional process steps or a change in the process sequence for the manufacture of the structure in a standard CMOS process, however, is not necessary in the above PCM structure in accordance with the recognition of the invention.
Only in this way is a monitoring of the production goods safeguarded, in particular in the processing of the wafer. The structure can thus be manufactured without additional expense on the one hand, while on the other hand it offers the only possibility of monitoring production goods during processing of the wafer without delaying the production sequence. In particular, the production goods can be continuously monitored in a cost-effective manner, and a continuous assessment of the charging can be carried out. In particular, expensive test wafers are avoided.
Further advantageous modifications of the invention as regards the structure in its first and second embodiment can be found in the dependent claims.
Preferably, a charge detector semiconductor component and/or a reference semiconductor component comprises a first region with the MOS field effect transistor and a first well, and a second region with the MOS capacitor and a second well, said first well and second well being doped with different signs. Favorably, the first well is a p-well and the second well an n-well. In particular, the MOS field effect transistor is an NMOS field effect transistor, and the MOS capacitor is a layered polycrystalline silicon/n-well capacitor.
In a further modification of the invention, the antenna, the capacitor gate, and the transistor gate are conductively interconnected, in particular connected with direct-contact conduction.
Advantageously, a control gate is formed by a well or by the source/drain contacts of the capacitor. This has the additional advantage that the storage cell can be read out in a particularly favorable manner.
Advantageously, furthermore, the transistor gate and the capacitor gate are each constructed as a polycrystalline silicon plate.
In particular, the structure of the first and of the second embodiment is arranged such that the semiconductor material is arranged in a first level, upon which the non-volatile storage cell is provided in a second level, on which second level the connections, the transistor gate, the capacitor gate, and the antenna or ground conductor are provided in a third level. It is found to be particularly favorable here that the transistor gate and the capacitor gate are jointly connected in one polycrystalline silicon level.
A construction in accordance with one of these modifications has the advantage that a manufacturing process for the structure is compatible with the CMOS-type manufacturing processes, in particular the standard CMOS process.
To achieve that the antenna dominates over the capacitor gate of the detector, advantageously, the surface area of the antenna is greater than the surface area of the polycrystalline silicon plate.
In a further series of modifications of the invention, the antenna may advantageously be implemented so as to be compatible with a standard CMOS technology. The antenna may be implemented as a polycrystalline silicon layer. In the CMOS-compatible implementation, the antenna is advantageously constructed in a single polycrystalline silicon layer. Alternatively, the antenna may be made of metal. In particular, the antenna may also be constructed as a contact antenna, in particular a via antenna. In another modification, the antenna is advantageously constructed as a MOS capacitor, in particular as an NMOS capacitor. It is safeguarded thereby that all levels in which charging can occur are monitored.
The invention further relates to a wafer in which the above characteristics of the embodiment of the invention can be realized. To achieve the object as regards the wafer, the invention provides a wafer, for example a silicon wafer, which, according to the invention, is fitted with a number of charge detector semiconductor components of the kind mentioned above and/or systems of the kind mentioned above. Advantageously, this is a production wafer, i.e. not a test wafer, on which the above structure is processed jointly with the production goods. The structure mentioned above may indeed have been manufactured already on the production wafer. In either case, the manufacture or processing takes place in a CMOS-type technology. This has the advantage that the structure is present on each production wafer. Preferably, the structure mentioned above is accommodated in a sawing lane of the wafer, which advantageously makes an effective use of the available space on the wafer. Processing of the production goods, in fact, takes place on the remaining region of the wafer. In a further embodiment of the invention, the above structure is manufactured and/or processed in accordance with a given area distribution on the wafer. This renders possible a measurement of charging which is subdivided as to areas and/or selective as to process steps.
To achieve the object as regards the use, according to the invention, a use of a wafer of the kind mentioned above with a plurality of charge detector semiconductor elements of the kind mentioned above and/or systems of the kind mentioned above for the qualitative and quantitative measurement of a charging, in particular plasma-induced charging, of the wafer during processing of the wafer is provided. In a further embodiment of the invention, a given area distribution of said plurality is provided for the measurement of a charging, in particular a plasma-induced charging, of the wafer during processing of the wafer, which measurement is subdivided as to areas and/or selective as to process steps.
The object of the invention is achieved as regards the method by means of a method for the qualitative and quantitative measurement of a charging, in particular a plasma-induced charging, of a wafer during processing of the wafer, wherein
the wafer is manufactured with the use of a CMOS-type technology,
the wafer is provided with a system comprising a charge detector semiconductor component and a reference semiconductor component during its manufacture, which charge detector semiconductor component comprises a non-volatile detector storage cell in the form of
a first MOS field effect transistor with a detector transistor gate, and advantageously also a source and a drain, and
a first MOS capacitor with a detector capacitor gate, and advantageously also a source and a drain, and
comprises an antenna which is connected to the detector capacitor gate by means of a first operational connection, wherein
the detector capacitor gate is connected to the detector transistor gate by means of a further first operational connection, and wherein
the reference semiconductor component comprises a non-volatile reference storage cell in the form of
a second MOS field effect transistor with a reference transistor gate, and advantageously also a source and a drain, and
a second MOS capacitor with a reference capacitor gate, and advantageously also a source and a drain,
and a ground conductor
which is connected to the reference capacitor gate by means of a second operational connection, while the reference capacitor gate is connected to the reference transistor gate by means of a further second operational connection, and the structure is arranged in accordance with a CMOS technology, such that
during processing the detector capacitor gate is charged via the antenna, and the reference capacitor gate is possibly charged, and the reference capacitor gate is discharged via the ground conductor, and
the charging of the detector capacitor gate is compared with the charging of the reference capacitor gate by means of a measurement.
Advantageously, the wafer is manufactured with a number of defined, locally distributed systems.
Further advantageous embodiments of the invention as regards the method are defined in the dependent claims.
In a further embodiment of the invention, the threshold voltage of the charge detector semiconductor component is compared with the threshold voltage of the reference semiconductor component for the measurement.
Alternatively, the drain currents may be compared while the control gate potentials applied to the charge detector component and the reference semiconductor component are the same. In such a case, in particular, the control gate potentials are formed by a well or by the respective source/drain connections of the capacitor of the detector semiconductor component and the reference semiconductor component.